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Tensilica Announces Availability of Atlas Reference Architecture Dataplane Processors for a Complete Baseband PHY for LTE, HSPA+ and WiMAX

(February 07, 2011)

SANTA CLARA, CA -- (Marketwire) -- 02/07/11 -- Tensilica®, Inc. today announced that all the optimized programmable DPUs (dataplane processing units) of its Atlas Reference Architecture are now available for customer evaluation. The Atlas Reference Architecture uses the Tensilica ConnX BBE16 baseband DSP (digital signal processor) core coupled with three function-specific dataplane processor cores to allow the baseband PHY (physical layer) SOC (system-on-chip) developer to create a very low power and minimal size PHY system, while enjoying the flexibility of a fully programmable radio, which is vital for competitive multi-standard user equipment devices (handsets) and femtocells. Atlas supports the 3GPP (3rd Generation Partnership Project) LTE (Long-Term Evolution) standard, as well as other complementary standards such as HSPA+ (Evolved High-Speed Packet Access) and WiMAX.

"Our LTE and HSPA+ products have propelled us as the leader for LTE baseband IP cores," stated Eric Dewannain, Tensilica's vice president and general manager of the Baseband Business Unit. "By completing our offering with these additional dataplane processors, we can help other LTE and HSPA+ chipset suppliers achieve a faster time-to-market, while also achieving very low power and minimal size."

"The ability to develop these optimized dataplane processors in a short time frame is a testimonial to the power of our patented DPU core foundation and tools which enables us to quickly create and optimize IP cores," he added.

The ConnX BBE16, introduced February 2010 (see press release dated February 8, 2010), is the single DSP part of the Atlas reference architecture, as it is built around a core vector pipeline made of sixteen 18bx18b MACs (multiply accumulators). ConnX BBE16 is optimized for performance of DSP kernel operations such as FFT (fast Fourier transform) and FIR (Finite Impulse Response) as well as matrix multiplies. This DSP core is optimized to give strong performance per power and area.

There are several other functions that must be implemented for a fully functional PHY system, and these are better implemented in function-specific DPUs to offer lower power and smaller size and address the control functions required. The three other Atlas components are:

  • The ConnX Soft Stream Processor (ConnX SSP16), a 16-way SIMD (single instruction, multiple data) baseband core optimized for the processing of soft bits, used for the acceleration of wireless communication PHY routines such as Viterbi, HARQ, and de-rate matching, as well as data manipulation and movement operations.
  • The ConnX Bit Stream Processor (ConnX BSP3), a baseband core optimized for the processing and control of bit streams, used for the acceleration of wireless communication PHY routines such as bit mapping, bit interleaving, and turbo encoding.
  • The multi-standard ConnX Turbo Decoder (ConnX Turbo16), a programmable turbo decoder for LTE and HSPA+ that achieves 150 Mbps decoded bit rate for LTE. The size of this multi-standard turbo decoder is in line with most RTL (register transfer level) hardware implementations in terms of power and area.

These Atlas dataplane processors offer superior performance per area and power for their specific operations, and are akin to hardware acceleration blocks that provide the post-silicon flexibility of a fully programmable processor. Coupled with the ConnX BBE16 DSP core, they offer leading class performance per area and power for a full LTE PHY implementation.

The ConnX SSP16 and ConnX BSP3 DPUs are available for evaluation now. The multistandard ConnX Turbo16 DPU will be available for evaluation June 2011.

About Tensilica
Tensilica, Inc. is the leader in customizable dataplane processor IP cores. Dataplane Processor Units (DPUs) combine the best capabilities of DSP and CPU while delivering 10 to 100x the performance because they can be optimized using Tensilica's automated design tools to meet specific signal processing performance targets. Tensilica's DPUs power SOC designs at system OEMs and six out of the top 10 semiconductor companies for products including mobile phones, consumer electronics devices (including digital TV, Blu-ray Disc players, broadband set top boxes, digital still cameras and portable media players), computers, and storage, networking, wireless base station and communications equipment. For more information on Tensilica's patented, benchmark-proven DPUs visit

Editors' Notes:

  • Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names are trademarks and/or registered trademarks of their respective owners.
  • Tensilica's announced licensees include: Afa Technologies, ALPS, Aquantia, Astute Networks, Atheros, AMD (ATI), Avision, Bay Microsystems, Brocade, Broadcom, Chelsio, Cisco Systems, CMC Microsystems, Conexant Systems, Design Art Networks, EE Solutions, Epson, Fujitsu Ltd., Fujitsu Microelectronics, HiSilicon division of Huawei, iBiquity Digital, Ikanos Communications, Intel, Juniper Networks, LG Electronics, Lucid Information Technology, Marvell, Maxim, NEC Corporation, Nethra Imaging, NuFront, Olympus Optical Co. Ltd., Panasonic Mobile, Plato Networks, PnpNetwork Technologies, PowerLayer Microsystems, QLogic, Samsung, SiBEAM, Sony, Stretch, TranSwitch Corporation, Triductor Technology, Valens Semiconductor, Validity Sensors, Victor Company of Japan (JVC), and Sirius XM Radio.

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