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Lattice Ships More Than 20 Million Programmable Mixed Signal Products

Programmable Mixed Signal Devices Lower Cost and Improve Time to Market (February 13, 2012)

HILLSBORO, OR -- (Marketwire) -- 02/13/12 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that it has shipped more than 20 million programmable mixed signal devices. Fast-growing, worldwide adoption is spread over key mixed-signal device families including the Lattice Power Manager II, the newly released Platform Manager, and ispClock™ families. Lattice programmable mixed-signal devices are used in a range of applications from low-cost solid state drives to complex high-end telecommunication infrastructure cards.

The Power Manager family was the first programmable mixed-signal device family created by Lattice. Responding to customer need for integration and true "management," Lattice defined the industry's first PLD-based flexible power management system: a fully integrated device providing hot-swap controller, voltage supervisor, reset generator, and sequencer ICs into a single chip solution that is significantly less expensive and more accurate than other solutions.

As circuit board control plane functionality became increasingly popular among the company's broad customer base, Lattice developed the Platform Manager family, extending the functionality of power management to include both power and digital management within a single-chip solution. All Power Manager II functions are supported in Platform Manager devices. Integration allows the Power Manager device to have a quick response time that enables the fault logging application to capture the initial error condition. Fault logging that is implemented with discrete ICs or a microprocessor is typically too slow to catch the initial event, making troubleshooting difficult.

As the complexity of SoCs continues to increase, efficient clock management becomes more difficult. In response to this challenge, Lattice created the ispClock family, a mixed-signal standard clock net solution device that fully integrates clock generators and clock distribution, providing a low-cost programmable skew solution. A single chip product, the ispClock device from Lattice replaces an assortment of zero delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts. Lattice's ispClock devices can be programmed in-system to generate multiple clock frequencies, compensate each output for differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signaling requirements.


"We used all of the resources available on the Power Manager POWR1014A device, from the on-board ADC to the MOSFET drivers," said Wayne Kuei, Research and Development Director, Advantech Co., Ltd. "The Power Manager device helped us achieve our goals of reduced cost, stability, functionality and simplified component sources, resulting in a simpler and more cost effective BOM."

"Customers are discovering that they can easily increase the reliability of their systems while reducing cost," said Shyam Chandra, Lattice Manager of Mixed Signal Solutions. "System reliability no longer needs to suffer from marginally designed power and platform management because of time and cost constraints. Our integrated solutions resolve many system problems that can often be traced back to an overlooked power management detail."

All mixed-signal product families are supported by customer proven development kits and reference designs enabling fast, easy product development.

For more information about Power Manager devices, visit www.latticesemi.com/powermanager; and for the new Platform Manager devices, visit http://www.latticesemi.com/products/powermanager/platformmanager/index.cfm; for information on the ispClock devices, visit www.latticesemi.com/ispclock. For details on the Hercules or Platform Manager Development kits, visit www.latticesemi.com/herculesdevkit or www.latticesemi.com/ptmdevkit.

Software Support
Designs for the Power Manager II, ispClock and Platform Manager devices are implemented using the Windows-based Lattice PAC-Designer® Software version 6.1 that is available for download free of charge from the Lattice website www.latticesemi.com/pac-designer.

About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com. Follow Lattice via Facebook, RSS and Twitter.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), PAC-Designer, ispClock, Platform Manager and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

EDITORIAL/READER CONTACT:
Doug Hunter
Vice President Corporate Marketing
Lattice Semiconductor Corporation
503.268.8512
doug.hunter@latticesemi.com


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