Company News: Page (1) of 1 - 10/29/01 Email this story to a friend. email article Print this page (Article printing at page facebook

Circuit Semantics and Mentor Graphics to Provide Automated DFT Solution for Custom Design

New capability will be demonstrated in the Mentor Graphics booth (No. 2401) at the International Test Conference (October 29, 2001)
Circuit Semantics and Mentor Graphics Corporation today announced an integrated Design-for-Test (DFT) solution that enables design and test engineers to create high coverage test vectors for custom transistor-level designs. As part of this solution, Circuit Semantics is introducing DynaTest, a new addition to its DynaModel product. DynaTest enhances the flow between transistor-level circuits and Mentor Graphics FastScan, the industry's leading automatic test pattern generation (ATPG) tool, and improves overall product quality by automatically creating optimized FastScan models from transistor-level circuits.

This new capability will be demonstrated in the Mentor Graphics booth (No. 2401) at the International Test Conference, October 30 - November 1, 2001.

The integration of the FastScan tool and the Circuit Semantics' DynaModel model generation solution automates the modeling process for transistor level circuits, significantly reducing the manual effort previously required for modeling full custom portions of a design. Furthermore, since DynaModel creates optimized models for FastScan, design and test engineers are assured that these models will provide the highest coverage test vectors possible.

"DynaModel eliminates the tedious task of manually creating models of our custom blocks for ATPG," said Thomas Dillinger, CAD manager for Sun's Processor Products Group. "By working together, Circuit Semantics and Mentor Graphics help Sun to more efficiently develop design flows which involve synergistic combinations of different EDA vendors."

Current methods for modeling and test generation of transistor-level circuits include manual remodeling, which is both time-consuming and prone to error, or modeling as transistors. Leaving circuits modeled as transistors for ATPG purposes often creates test generation problems and reduces test coverage for those portions of the design. Through the integration of FastScan and DynaModel, Spice netlists are remodeled directly for FastScan, eliminating the need for manual intervention. Additionally, the creation of DFT-specific models optimized for FastScan and ATPG improves test coverage. This capability will greatly reduce the engineering time associated with generating test patterns for custom designs.

"Collaborating with Mentor Graphics provides customers with a solution that bridges the gap between custom and gate level design," said Gary Larsen, president and CEO of Circuit Semantics. "Our complementary technology and close working relationship ensures our mutual customers will receive an automated ATPG flow."

"FastScan is the test pattern generation tool of choice for microprocessor designers where custom design is most prevalent," said Lori Watrous-deVersterre, general manager, Mentor Graphics Design-for-Test division. "This agreement with Circuit Semantics enables us to provide an automated design-for-test flow for custom design, demonstrating Mentor's leadership and commitment to this market segment."

DynaModel is priced at $95,000 for a single user floating license and DynaTest is priced at an additional $40,000. Both prices are US domestic prices. FastScan product upgrades are not required to take advantage of this integrated flow. DynaModel and DynaTest are currently available.

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $600 million and employs approximately 2,975 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, OR 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, CA 95131-2314. World Wide Web site:

Founded in 1997, Circuit Semantics is a team of highly skilled engineers, inventors, and management professionals. Circuit Semantics has designed, produced, and managed a set of widely accepted EDA products for the semiconductor industry. At Circuit Semantics, the collective powers of the corporate team and our customers have provided the technology and products for the microprocessors, digital signal processing, graphics, and high-speed communication markets.

Circuit Semantics simplifies the tasks of designing high performance ICs that use complex logic techniques. Our approach brings "ASIC-like" productivity levels to custom design, and the performance and accuracy of custom designs to ASICs.

Headquartered in San Jose, Calif., with sales and customer support offices worldwide, Circuit Semantics is a privately held company. Corporate headquarters are located at 2590 North First St., San Jose, CA 95131. An Austin Texas facility is located at 1301 Capitol of Texas Hwy, Bldg B, Suite 310, Austin, TX 78746. World Wide Web site:

Page: 1

Related Keywords:Circuit Semantics, Mentor Graphics, CAD


Our Privacy Policy --- @ Copyright, 2015 Digital Media Online, All Rights Reserved