DAC Booth # 1930 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff.

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Cadence Encounter and Virtuoso Design Platforms Receive TSMC 20nm Phase I Certification

Cadence 20-nanometer Readiness for Digital, Custom/Analog and Signoff (June 04, 2012)

SAN FRANCISCO, CA -- (Marketwire) -- 06/04/12 -- DAC Booth # 1930 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff.

TSMC certified the tools for 20-nanometer design rule manuals (DRMs) and SPICE models. Early adopters are using the flows and tools while close collaboration continues between TSMC, Cadence and designers.

The Cadence Encounter® RTL-to-GDSII digital flow includes support for 20-nanometer rules, and innovative patterning placement, optimization, clocking, and routing. For custom/analog, certification covers advanced Virtuoso SKILL Pcell abutment to address complex device-level rules, and in-design loop detection using signoff quality DRC with the integrated Cadence Physical Verification System (PVS).

In signoff, Cadence QRC Extraction and Cadence PVS, including full DRC/LVS physical verification, and Encounter Power System for electromigration and IR have been certified. The companies are working toward certification for Encounter Timing System.


"Close collaboration with TSMC and joint R&D efforts have led to this important milestone," said said Dave Desharnais, group director of product marketing, Silicon Realization Group. "We are working closely with the world's leading semiconductor companies, and this certification helps pave the way for them to reap the benefits of a smooth transition to the 20-nanometer node."

"TSMC certification is an important milestone for 20-nanometer readiness," said Suk Lee, senior director of Design Infrastructure Marketing at TSMC. "Our ongoing work with Cadence demonstrates how collaboration accelerates innovation and benefits the advanced design community."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com


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