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Cadence Announces Updated Design and Verification IP for DDR PHY Interface

Cadence IP Now Supports DFI 3.1 Standard, Including Support for LPDDR3 Memory (May 29, 2012)

SAN JOSE, CA -- (Marketwire) -- 05/29/12 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that the company's comprehensive suite of DDR controller and DDR PHY design IP as well as its Cadence Verification IP Catalog now support the latest release of the DFI specification, version 3.1 (also announced today by the DFI Group). The new version adds support for the LPDDR3 mobile memory standard for smartphones and tablets, and includes enhancements to the PHY's low-power interface and training features. The DFI interface standard was developed through the collaborative effort of leaders in the semiconductor and EDA markets and has become the de facto industry standard for high-bandwidth memory interfaces.

"As the performance of the processors used in today's consumer electronics devices improves, so does their need for higher-bandwidth memory. The DFI interface standard was developed to give SoC designers a way to easily incorporate high-performance memory into their SoCs," said Marc Greenberg, director of marketing, SoC Realization, Cadence. "Through our close working relationship with the DFI Group, we are able to offer our customers design and verification IP that supports the latest version of this popular interface standard."

Cadence has over 400 design wins for DDR controllers and PHYs, and all DDR3 designs currently in development use the DFI interface. With the addition of support for LPDDR3 memory, the DFI standard can now be used in the development of SoCs targeting smartphone and tablet applications that require higher-bandwidth memory. The standard has been recognized by JEDEC, the microelectronics industry's open standards organization.

About DFI 3.1
DFI 3.1 is a memory interface standard that enables the interoperability of IP between different companies. It defines methods for interfacing to DDR4 devices (with data rates up to 3.2 Gbits/second per pin) and LPDDR3 devices (with data rates up 6.4 Gbits/sec. and 12.8 Gbits/second for a dual channel configuration). The preliminary specification is available now for download at www.ddr-phy.org.


About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
dsolov@cadence.com (e-mail)
408-944-7226 (phone)


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