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At DAC, Docea Power Showcases Electronic System Design (ESL) Solutions for Power and Thermal Analysis and Modelling; Program Features Docea & User PresentationsFocus Is on How to Model and Optimize Power and Thermal Management Policies of SoC and Chipsets Designs (May 30, 2012)
SAN FRANCISCO, CA -- (Marketwire) -- 05/30/12 --
At the Design Automation Conference (DAC) in San Francisco, Docea Power, the design-for-low-power company that delivers ESL tools for power and thermal analysis and modelling, is demonstrating how to use its Aceplorer® for early power architecture exploration and validation, power budget tracking and coupled power and thermal simulation.
The User Track presentations at DAC include talks from Huawei Technologies and STMicroelectronics co-authored by Docea Power.
A Docea speaker is also presenting at the ARM Connected Community Pavilion.
Monday-Wednesday, June 4-6, from 9 am to 6 pm
Docea Booth #1702
ARM Connected Community Pavilion Presentation
Tuesday, June 5, 2012, 5 pm
ESL power modelling and optimization for ARM-based SoC architectures
Christophe Lucarz, PhD, Field Application Engineer, Docea Power
Booth # 802
User Track Presentations:
Thursday, June 7, 2012 from 1:30 pm-3 pm, Room 303
An ESL Power Flow for Optimizing and Validating the Power Management Strategy on a Multi-Core SoC
Xiaotao Chen, Huawei Technologies Co., Ltd., Bridgewater, NJ
Co-Simulation of a SystemC TLM Virtual Platform with a Power Simulator at the Architectural Level: Case of a Set-Top Box
Jerome Cornet, STMicroelectronics, Grenoble, France
Moscone Convention Center, San Francisco, California
For More Information
For more information about Docea Power, please visit www.doceapower.com
To set an appointment with Docea, please click here.
For more information about DAC, please visit www.dac.com
About Docea Power
Docea Power develops and commercializes a new generation of methodology and tools for enabling faster and more reliable power and thermal modelling at the Electronic Systems Level (ESL). Docea's solutions offer a consistent approach for architectural exploration and optimizing power and thermal behaviour of electronic systems, at an early stage of an electronic design project. Customers include manufacturers of electronic systems, chips and boards that target wireless, multimedia, consumer, networking and automotive applications.
The company has offices near Grenoble, France, and in San Jose, California, USA, and sales offices in Japan and Korea. For more information: www.doceapower.com.
Acronyms and Definition
ESL: Electronic System Level
TLM: Transaction Level Modelling
Aceplorer and AceThermalModeler are trademarks of Docea Power.
All other trademarks or tradenames are the properties of their respective owners.
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